![]() ![]() For example, if the accumulator contains a binary number that is known to be less than 100 10, it is quickly converted to BCD as follows:ĭividing the number by 10 in the first two instructions leaves the tens digit in the low nibble of the accumulator, and the ones digit in the B register. This is a useful operation BCD manipulation. The SWAP A instruction exchanges the high and low nibbles within the accumulator. The carry flag rotates into ACC.7 and ACC.0 rotates into the carry flag. ![]() Leaves the carry flag clear and A equal to 80H. If, for example, the carry flag contains 1 and A contains 00H, then the instruction The RLC A and RRC A variations are 9-bit rotates using the accumulator and the carry flag in the PSW. For a right rotation, the LSB rolls into the MSB position. For a left rotation, the MSB rolls into the LSB position. The rotate instruction (RL A and RR A) shift the accumulator one bit to the left or right. Since the eight bits of immediate data are all 1s, the effect is to complement each bit read (e.g., A OR 1 = Ᾱ). The eight bits at Port 1 are used then each bit read is exclusive ORed with the corresponding bit in the immediate data. This instruction performs a read-modify-write operation. The “XRL direct, #data” instruction offers a quick and easy way to invert port bits, as in Logical operations can be performed on any byte in the internal data memory space without going through the accumulator. Since the addressing modes for the logical instructions are the same as those for arithmetic instructions, the AND logical instruction can take several forms:Īll logical instructions using the accumulator as one of the operands execute in one machine cycle. Leaves the accumulator holding 00010001B. If the accumulator contains 00110101B, then the following AND logical instruction The 8051 logical instructions perform Boolean operations (AND, OR, Exclusive OR, and NOT) on bytes of data on a bit-by-bit basis. For example, if A contains the BCD value 59 (59H), then the instruction sequence ![]() Note that DA A will not convert a binary number to BCD it produces a meaningful result only as the second step in the addition of two BCD bytes. (25 / 6 = 4 with a reminder of 1.)įor BCD (binary-coded decimal) arithmetic, ADD and ADDC must be followed by a DA A (decimal adjust) operation to ensure the result is in range for BCD. The A accumulator is left with the value 4 and B accumulator is left with the value 1. For example if A contains 25 (19H) and B contains 6 (06H), the instructionĭivides the content of A by the content of B. DIV AB divides the accumulator by the data in the B register, leaving the 8-bit quotient in the accumulator and the 8-bit remainder in the B register. The MULAB instruction multiplies the accumulator by the data in the B register and puts the 16-bit product into the concatenated B (high-byte) and accumulator (low-byte) registers. The high- and low-bytes of the DPTR must be decremented separately however, the high-byte (DPH) is only decremented if the low-byte (DPL) underflows from 00H to FFH. Unfortunately, a decrement data pointer instruction is not provided and requires a sequence of instructions such as the following:ĬJNE R7, #OFFH, SKIP IF UNDERFLOW TO FF Since the data pointer generates 16-bit addresses for external memory, incrementing it in one operation is a useful feature. One of the INC instructions operates on the 16-bit data pointer. Increments this value, leaving 41H in location 7FH. For example, if internal RAM location 7FH contains 40H, then the instruction ![]() Any location can be incremented or decremented using direct addressing without going through the accumulator. The 8051 provides powerful addressing of its internal memory space. (Note that one machine cycle takes 1 micro sec if the 8051 is operating from a 12 MHz clock.) Since four addressing modes are possible, the ADD A instruction can be written in different ways:Īll arithmetic instructions execute one machine cycle except the INC DPTR instruction (two machine cycles) and the MUL AB and DIV AB instructions (four machine cycles). The arithmetic instructions are grouped together in Appendix A. The 8051 micro-controller instructions are divided among five functional groups: ![]()
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